Exposure control for phase shifting photolithographic masks

ABSTRACT

Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0&lt;r&lt;4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

RELATED APPLICATIONS

[0001] This application is related to, claims the benefit of priorityof, and incorporates by reference, the U.S. Provisional PatentApplication Serial No. 60/296,788 filed Jun. 8, 2001 entitled “PhaseConflict Resolution for Photolithographic Masks” having inventorsChristophe Pierrat and Michel Côtéand assigned to the assignee of thepresent invention.

[0002] This application is related to, claims the benefit of priorityof, and incorporates by reference, the U.S. Provisional PatentApplication Serial No. 60/304,142 filed Jul 10, 2001 entitled “PhaseConflict Resolution for Photolithographic Masks” having inventorsChristophe Pierrat and Michel Côté and assigned to the assignee of thepresent invention.

COLOR DRAWINGS

[0003] The file of this patent contains at least one drawing executed incolor. Copies of this patent with color drawing(s) will be provided bythe Patent and Trademark Office upon request and payment of thenecessary fee.

BACKGROUND OF THE INVENTION

[0004] 1. Field of the Invention

[0005] The present invention relates to manufacturing small dimensionfeatures of objects, such as integrated circuits, usingphotolithographic masks. More particularly, the present inventionrelates to the application of phase shift masking to complex layouts forintegrated circuits and similar objects.

[0006] 2. Description of Related Art

[0007] Phase shift masking has been applied to create small dimensionfeatures in integrated circuits. Typically the features have beenlimited to selected elements of the design, which have a small, criticaldimension. See, for example, U.S. Pat. No. 5,766,806.

[0008] Although manufacturing of small dimension features in integratedcircuits has resulted in improved speed and performance, it is desirableto apply phase shift masking more extensively in the manufacturing ofsuch devices. However, the extension of phase shift masking to morecomplex designs results in a large increase in the complexity of themask layout problem. For example, when laying out phase shift windows ondense designs, phase conflicts will occur. One type of phase conflict isa location in the layout at which two phase shift windows having thesame phase are laid out in proximity to a feature to be exposed by themasks, such as by overlapping of the phase shift windows intended forimplementation of adjacent lines in the exposure pattern. If the phaseshift windows have the same phase, then they do not result in theoptical interference necessary to create the desired feature. Thus, itis necessary to prevent inadvertent layout of phase shift windows inphase conflict near features to be formed in the layer defined by themask.

[0009] In the design of a single integrated circuit, millions offeatures may be laid out. The burden on data processing resources foriterative operations over such large numbers of features can be huge,and in some cases makes the iterative operation impractical. The layoutof phase shift windows and the assignment phase shift values to suchwindows, for circuits in which a significant amount of the layout isaccomplished by phase shifting, is one such iterative operation whichhas been impractical using prior art techniques.

[0010] Another problem that is associated with the use of phase shiftmasking arises from the need for two different mask patterns forimplementation of a layer of material having small dimension features.Existing systems expose the wafer using a binary mask pattern using astepper having optical settings optimized for the binary mask pattern,and expose the wafer using the phase shift mask pattern using a stepperhaving optical settings optimized for the phase shift mask pattern.Typically, the optical settings are quite different. For example, aphase shift pattern is usually exposed using a highly coherent radiationsource. However, binary masks achieve better results having lesscoherent radiation sources. Thus, between the two exposures, the waferis required to sit while the settings and masks are changed within thestepper. During the time the wafer sits, the quality of the resist candegrade. Furthermore, the time involved in moving the wafer andadjusting a stepper slow down the manufacturing process. For backgroundconcerning optical lithography and the phase shift masking, see Wong,RESOLUTION ENHANCEMENT TECHNIQUES IN OPTICAL LITHOGRAPHY, SPIE Press,Bellingham, Wash. (2001).

[0011] It is useful to understand the common stepper settings andparameters used in so called “gate shrink” phase shifting designs. A“gate shrink” design, or mask, is simply a layout, or mask, wheresignificant portions of a pattern, usually field polysilicon, must stillprint properly using the corresponding binary trim mask, while portionssuch as transistor gates are formed using phase shifting, resulting inso-called “shrunk” gates.

[0012] Generally, phase shifting masks require a low partial coherence σarrangement in the stepper, so that the light exposing the wafer ishighly coherent.

[0013] In contrast, when working with a binary pattern on a mask thathas densely packed and small features, high partial coherence σ steppersettings producing less coherent light, and/or off-axis-illumination(OAI), or other illumination configurations are employed.

[0014] For that reason, the binary trim pattern on a mask for a gateshrink-type design would commonly be exposed using low coherency (highσ) or off-axis illumination. But, the phase shifting pattern on a maskfor such a gate shrink-type design would use high coherency (low σ)illumination. This requires an adjustment of the projection system inthe stepper, typically a change in size of an aperture, between thephase shifting pattern and trim pattern exposures.

[0015] Because of these and other complexities, implementation of aphase shift masking technology for complex designs will requireimprovements in the approach to the design of phase shift masks.

SUMMARY OF THE INVENTION

[0016] Mask and integrated circuit fabrication approaches are describedto facilitate use of so called “full phase shift” masks, wheresubstantially all of a layout is defined using phase shifting.Definitions of other patterns, layouts, and mask types for which theinvention is suitable are described below.

[0017] For the masks used by embodiments of the invention, the opticalsettings of a stepper are maintained constant, except for dosing in someembodiments, between exposure with the phase shifting pattern and thebinary trim pattern. Optical settings that are not changed between theexposures of the phase shifting and trim patterns include one or moremembers of a set of optical parameters including numerical aperture(N.A.), wavelength (λ) of light, coherency (such as measured by partialcoherence σ), illumination configuration (single spot source, dipolesource, quadrapole source, annular source), axis of illumination, anddefocus, in various combinations.

[0018] In various embodiments, the relative dosing between the exposureof the phase shifting pattern and the trim pattern is expressed by aratio 1.0:r, where r>0.0. In some embodiments, 2.0<r<4.0, so that theexposure dosing of the binary pattern is from 2 to 4 times greater thanthe dosing of the phase shifting pattern. One embodiment uses a 1:2ratio, another a 1:3 ratio. The greater exposure of the trim patternfacilitates clearing of cuts, or openings, while preventing exposure ofthe features defined by the phase shifting pattern. In some embodiments,r is determined from simulation results for a particular opticallithography model, e.g. stepper, wavelength, resist measurements, etc.

[0019] Additionally, both patterns are provided on a single reticle inone embodiment of the present invention. A single reticle with multiplepatterns can increase mask manufacturing costs. However, the cost of themask is justified because the use of the single reticle can improveyield, and save manufacturing steps and time. A multiple pattern reticlecan allow more rapid exposure of the layer of material using both thephase shifting pattern and the trim pattern. The layout of patterns onthe single reticle can be simple (one of each) or more complex (multiplephase patterns; multiple binary patterns; one-dimensional;two-dimensional; etc.) The dosing ratio r for a layer to be exposed canbe implemented, for example using constant exposure doses to eachpattern with the ratio of the number of phase shifting patterns and tothe number of trim patterns on the mask set equal to the dosage ratio1.0: r. In this example, the exposure dosage is another parameter thatis not changed between exposures of the phase shift and trim patterns.

[0020] A method for manufacturing an integrated circuit is providedaccording to the present invention, which includes forming a layer ofresist on a semiconductor wafer, moving the wafer to a stepper systemincluding a radiation source and a reticle having a phase shiftingpattern and a trim pattern; positioning the wafer and the reticle forexposure of a phase shifting pattern in the reticle; applying a dose ofradiation to the wafer through the phase shifting pattern using steppersettings including a set of optical parameters including numericalaperture (N.A.), wavelength (λ) of light, coherency (such as measured bypartial coherence σ), illumination configuration (single spot source,dipole source, quadrapole source, annular source), axis of illumination,and defocus; positioning the wafer and the reticle for exposure of atrim pattern in the reticle; applying a dose of radiation to the waferthrough the trim pattern using stepper settings including said set ofparameters for the trim exposure, wherein all or some of the members ofsaid set of parameters are substantially the same as those used for thephase shifting exposure. The phase shifting and trim patterns may beexposed in any order that results in the die on the wafer being exposedusing both, and receiving proper dosages of radiation for the phaseshifting and trim patterns. After exposing both patterns, the wafer isremoved from the stepper, and available for subsequent steps to completethe integrated circuit. Then, the stepper is available for a next waferin the line.

[0021] In one embodiment, all of said stepper settings are the same, inthe sense that the stepper settings are not altered, or in otherembodiments, settings of parameters that involve changing or moving anoptical device such as an aperture stop setting or a lens position arenot changed, between the phase shifting and trim exposures. In someembodiments, one reticle carries the phase shifting pattern and anothercarries the trim pattern, and the steps of positioning the reticle andthe wafer include selecting the appropriate reticle.

[0022] In one embodiment, after exposing both patterns, the photoresistis developed, and the resulting pattern of developed photoresist is usedfor formation of a layer of polysilicon on the wafer, including elementsof circuits being formed thereon. Such elements include transistorgates, interconnect structures, and the like.

[0023] Resulting ICs produced according to embodiments of the inventioncan include a large number of subwavelength features due to the use ofphase shifting and those features will tend to be extremely well definedbecause of the high quality energy profile achieved, and the ability torapidly develop the photoresist by using embodiments of the invention(shorter and more uniform time intervals between exposures; fewermistakes in lithography settings, fewer mistakes in optical settings;etc.)

BRIEF DESCRIPTION OF THE FIGURES

[0024] The file of this patent contains at least one drawing executed incolor. Copies of this patent with color drawing(s) will be provided bythe Patent and Trademark Office upon request and payment of thenecessary fee.

[0025]FIG. 1 illustrates a pattern of features and phase shift regionsfor defining those features.

[0026]FIG. 2 illustrates a simulated exposure of the layout of FIG. 1according to a 1:2 dosage ratio between the phase shifting mask and thetrim mask.

[0027]FIG. 3 illustrates a simulated exposure of the layout of FIG. 1according to a 1:1 dosage ration between the phase shifting mask and thetrim mask.

[0028]FIG. 4 illustrates a single reticle having both a phase shiftingand trim patterns.

[0029]FIG. 5 illustrates a portion of a wafer after a first exposure bythe reticle of FIG. 4.

[0030]FIG. 6 illustrates the wafer of FIG. 5 after a second exposure bythe reticle of FIG. 4.

[0031]FIG. 7 illustrates a portion of a wafer after a first exposure bythe reticle of FIG. 4 with blading.

[0032]FIG. 8 illustrates the wafer of FIG. 7 after a second exposure bythe reticle of FIG. 4 with blading.

[0033]FIG. 9 illustrates a single reticle having phase shifting patternand two trim patterns.

[0034]FIG. 10 illustrates a portion of a wafer after a first exposure bythe reticle of FIG. 9.

[0035]FIG. 11 illustrates a portion of a wafer after a second exposureby the reticle of FIG. 9.

[0036]FIG. 12 illustrates a portion of a wafer after a third exposure bythe reticle of FIG. 9.

DETAILED DESCRIPTION Overview

[0037] First, exposure settings for use in conjunction with phaseshifting masks that produce substantial portions of a pattern of a layeron an integrated circuit (IC) using phase shifting will be considered.Next, relative dosing considerations between the phase shifting patternexposure and the binary, trim pattern exposure will be considered.Finally, approaches for using a single reticle in the production of ICsusing phase shifting will be considered. (As used herein, the terms“mask” and “reticle” are synonyms, generally referring to a devicecarrying patterns, also called layouts, for photolithographic exposureused in manufacture of semiconductor wafers or other workpieces.)

Exposure Settings

[0038] In one embodiment of the invention, an optical lithographyexposure system, generally referred to as a stepper, has a setting ofmembers of a set of one or more optical parameters that controlcharacteristics of exposures, the settings used to expose the phaseshifting pattern and the complementary trim pattern used to produce anIC using phase shifting are unchanged, or otherwise kept substantiallythe same, between the exposures. This is applied for example when all,or substantially all portions, of a pattern are being defined using aphase shifting pattern on a mask, because there is minimal need to printsmall features using the trim pattern. Thus the trim pattern consists offeatures that have greater design latitude in exposure settings that dothe features formed using the phase shifting pattern, and can be exposedwith key optical settings such as one or more members of a set ofoptical parameters including numerical aperture (N.A.), wavelength (λ)of light, coherency (such as measured by partial coherence σ),illumination configuration (single spot source, dipole source,quadrapole source, annular source), axis of illumination, and defocus,in various combinations.

[0039] Masks having a phase shift pattern that results in all, orsubstantially all portions, of a pattern on the layer of material beingexposed being defined using the phase shifting pattern, are sometimesreferred to as “full phase” masks. In one embodiment, the masks aredefined according to the process described in U.S. patent applicationSer. No. 09/932,239 filed Aug. 16, 2001, entitled “Phase ConflictResolution for Photolithographic Masks” having inventors ChristophePierrat and Michel Côtéand assigned to the assignee of the presentinvention, which is incorporated herein by reference as if fully setforth herein.

[0040] In another embodiment, a phase shifting mask that producessubstantial portions of a pattern of an IC using phase shiftingcomprises a phase shifting pattern on the mask where substantially allfeatures for a particular layer are defined using phase shifting. Inanother embodiment, a phase shifting mask that produces substantialportions of a pattern of an IC using phase shifting comprises a patternon a mask such that only features that are non-critical for the binaryexposure are non-phase shifted. In such an embodiment, a non-criticalfeature is a feature where there is greater latitude in criticaldimension control such that when the non-critical feature is exposedaccording to the conditions more fully described below the resultingcritical dimension variances are acceptable.

[0041] In other embodiments, the relevant layout comprises a layoutwhere phase shifting is used to define at least one of:

[0042] eighty percent (80%) of non-memory portions in one layer ofmaterial in the layout;

[0043] eighty percent (80%) of a part of the floorplan in one layer ofmaterial;

[0044] eighty percent (80%) of cells in a given area;

[0045] ninety percent (90%) of a layer of material;

[0046] ninety five percent (95%) of a layer of material;

[0047] ninety nine percent (99%) of a layer of material;

[0048] one hundred percent (100%) of a layer of material;

[0049] one hundred percent (100%) of a in a functional unit of the chip(e.g. ALU) in one layer of material;

[0050] one hundred percent (100%) of features in a layer of materialthat are in the critical path of the design;

[0051] one hundred percent (100%) of features in a layer of materialabove or below certain dimensions, e.g. all features with a criticaldimension 50 μm<CD<100 μm;

[0052] everything in a layer of material except those features thatcannot be phase shifted due to phase conflicts that cannot be resolved;

[0053] everything in a layer of material except test structures; and

[0054] one hundred percent (100%) of all non-dummy features, e.g.features providing structural support for processing purposes, andnon-electrically functional features in a layer of material.

[0055] By maintaining a high coherency illumination setting (low partialcoherence σ) for both the phase shifting and binary trim pattern on amask, it is possible to more quickly, and accurately, produce ICs whereall or substantially of the pattern features are defined using phaseshifting. In one embodiment, the percentages are determined based on thenumber of edges, or edge segments, within the pattern defined usingphase shifting.

[0056] In one embodiment, one or more of the numerical aperture (NA) ofthe radiation exposing the wafer, the coherency setting (σ), theillumination configuration (on/off axis, dipole, quadrapole, annular,etc.), and defocus are kept unchanged between the phase shifting andtrim exposures. In one embodiment, all optical settings that requiremechanical adjustment of items in the optical path to change, such as anaperture stop setting, or a lens position, are left unchanged betweenthe phase shifting and trim pattern exposures.

[0057] In one embodiment, keeping the stepper settings unchangedfacilitates the use of the single reticle approach described below. Inanother embodiment, keeping the stepper settings unchanged facilitatesthe use of a single stepper for exposure of both the phase shiftingpattern and the corresponding trim pattern, whether such patterns are onthe same mask or on separate masks.

Dosing

[0058] Turning to FIG. 1, a pattern of features and phase shift regionsfor defining those features is shown. The phase shifting design shown inFIG. 1 was manually defined. The pattern includes the feature 100 andthe feature 102. Of interest is the proximity of the end cap of thefeature 100 with the top edge of the feature 102. The phase shiftregions have been defined with the shifter 104, the shifter 106, theshifter 108, and the shifter 110. Here, the shifter 106 and the shifter110 share a single phase, e.g. 0, as do the shifter 104 and the shifter108, e.g. π.

[0059] Turning to FIG. 2 and FIG. 3, simulation results for the patternof FIG. 1 are shown with stepper settings maintained constant, but therelative dosing between pattern exposures changed. FIG. 2 shows asimulation output 200 where the relative dosing between the phase shiftpattern and the corresponding trim pattern was 1:2 (r=2). FIG. 3 shows asimulation output 300 where the relative dosing was 1:1 (r=1).

[0060] Looking more closely at the simulation output 200 and thesimulation output 300, the outputs include black contour lines (contourline 202, contour line 204, contour line 302, and contour line 304) thatindicate where the feature 100 and the feature 102 will print. As can beseen from the figure, with a 1:1 ratio, FIG. 3, the end cap of thefeature 100 and the edge of the feature 102 come extremely close. Incontrast, with a 1:2 ratio, FIG. 2, the end cap and edge are betterdefined, and therefore less likely to improperly print as a singleconnected feature.

[0061] More generally, higher values of r in the ratio 1.0:r, wherer>1.0 are useful in printing ICs when phase shifting masks of the typediscussed here are used. In one embodiment, 2.0<r<4.0. In anotherembodiment, a 1:3 ratio is used. Most generally, r can have a realnumbered value as the stepper/scanner exposure setting will be set in anabsolute number of millijoules per square centimeter per exposure, e.g.10 mJ/cm²and 20 mJ/cm², etc.

[0062] In some embodiments, one or more simulations are performed usingthe actual and/or test layouts to select r for a particularoptical/stepper model. However, the selected ratio reflects a balancebetween “hard” or over exposure for cut regions (necessary anddesirable) versus exposure of areas under the trim (undesirable).

Single Reticle

[0063]FIG. 4 illustrates a single reticle having both a phase shiftingand trim patterns. In this example, the reticle 400 includes a phaseshifting pattern 402 and a trim pattern 404. The phase shifting pattern402 shows a pattern “1” and the trim pattern 404 a pattern “2” forconvenience of explanation of the wafer exposures described below.

[0064] The phase shifting pattern 402 and the trim pattern 404 areseparated by a small gap. In some embodiments, the gap is dependent onthe blading capabilities and accuracy for the stepper. In oneembodiment, the separation is 5 mm.

[0065] A given stepper/scanner system will have a usable area of a mask,e.g. an n by m millimeter field. Thus, the number of mask patterns thatcan be accommodated on a single reticle will depend on the size of thedesign and the usable reticle area.

[0066] In one approach, the dosing will be maintained at equal levelsfor the trim and binary exposures. Turning to FIG. 5, a wafer 500 isshown after the first exposure. The wafer 500 has the alternating 1-2pattern caused by the exposure of some regions to the phase shiftingpattern and the exposure of other regions to the trim pattern 404. Asecond exposure, shown in FIG. 6, of the wafer 500 completes the processonce the reticle and/or wafer has been repositioned within the stepper.FIG. 6 illustrates the pattern as 12 or 21 depending on the order ofexposure for a region.

[0067] In another approach, dosing can be at a user selected ratio, e.g.1.0:r, between patterns through the use of blading. By blading, orcovering, one region of the reticle 400, an exposure of the type shownin FIG. 7 on a wafer 700 will result after all of the fields on thewafer are exposed. A second exposure after repositioning the reticleand/or wafer in the stepper is shown in FIG. 8 where the exposure withthe phase shifting pattern 402 is complete. The blades could then beadjusted to cover the other patterns of the reticle and allow exposuresto be made with the trim pattern 404 exposing the wafer.

[0068]FIG. 9 illustrates a single reticle having phase shifting patternand two trim patterns. In this example, the reticle 900 includes a phaseshifting pattern 902, a trim pattern 904 and a trim pattern 906. In thisembodiment, the trim pattern 904 and the trim pattern 906 are designedto produce the same pattern. Accordingly, by triple exposing the wafer a1:2 dosing ration between the phase shifting pattern and the trimpatterns can be accomplished. The results are depicted in FIGS. 10-12showing a portion of the wafer after the first exposure 1000, after thesecond exposure 1100, and after the third exposure 1200, respectively.

[0069] More complex reticle patterns are possible. For example, twophase shifting patterns could be used, e.g. with one phase shiftingpattern having structures in one orientation and another pattern withstructures in another orientation. In other embodiments, atwo-dimensional pattern of the mask patterns on the reticle is used.

[0070] The present invention also provides method for manufacturing anintegrated circuit. Method includes forming a layer of resist on a waferat a first process station. The resist is cured and prepared forexposure using a stepper or scanner. The wafer with a layer of resist istransported to the stepper. The stepper includes a radiation source, amask and an optical path for exposing the wafer to radiation. Theoptical path is characterized by a set of optical parameters includingone or more of a wavelength λ of illumination, numerical aperture NA,coherency, illumination configuration and defocus. In the stepper, thelayer of resist is exposed to a first dosing radiation to a phaseshifting pattern in said mask using a first setting of the set ofoptical parameters. Next, the layer of resist is exposed to a seconddose of radiation through the trim pattern in said mask using said firstsetting. Thus, the setting of the optical parameters is not changedbetween the exposures of the phase shift pattern and the trim pattern.As mentioned above, the mask may have more than one trim pattern andmore than one phase shift pattern implemented thereon. In this case, thewafer may be subject to additional exposure steps, in which the settingsof the optical parameters are not changed. The order of exposure of thephase shift pattern or patterns and trim pattern or patterns can bechanged as suits a particular processing situation.

[0071] As can be seen, according to this process both the phase shiftand trim exposures are carried out in the same stepper, using the samesettings. Thus, the wafer does not wait for changing of opticalparameters, or to be moved from one stepper to the next, betweenexposures. This reduces the possibility for error in manufacturing ofthe device, and reduces the time required to complete the exposure step.

[0072] After the exposure, the resist is developed using the techniquesthat are adapted for use with a particular resist involved. A pattern isleft on the wafer which is used for a deposition and/or etching step toform of features an integrated circuit. For example, the pattern may beused for etching an underlying layer of polysilicon to forminterconnect, gate, capacitor, resistor and other circuit features onintegrated circuit.

Process Advantages

[0073] Maintaining the stepper settings as a constant can significantlyimprove throughput as well as lead to better critical dimensionuniformity. Accordingly, if too much time passes between the firstexposure and the second exposure and/or the amount of time is notmaintained constant the results may be poorer than expected.

[0074] More specifically, current generation photoresist materials arechemically amplified so that exposure to light produces a very smallnumber of acid molecules, that then continue to react. The passage oftime and exposure to air may cause carbon dioxide, and other chemicals,to take up the acid and neutralize it. Using the single reticleapproach, the photoresist should maintain its properties throughout bothexposures and the timing between exposures can be shorter and moreclosely controlled the effect of exposure. Additionally, over time, theacid diffuses into the polymer.

[0075] The better effects from different dosing can be implemented whilemaintaining other stepper settings constant.

[0076] The increased throughput and yield possible should readily makeup for the increase in reticle costs; although, the cost should becomparable, or less than, the cost of a dual reticle approach usingseparate masks for phase shifting and binary patterns.

Representative Alternative Embodiments

[0077] Additionally, although the description has primarily focused onexamples of defining a polysilicon, or “poly”, layer within an IC, phaseshifting can be used to define other layers of material.

[0078] Some embodiments of the invention include computer programs forsimulating stepper exposures using phase shift and trim patterns tocompute appropriate relative dosing between phase and trim/binaryexposures. In one embodiment, the ICWorkbench(™) software produced byNumerical Technologies, Inc., San Jose, Calif. is used to simulate theexposure conditions, e.g. as seen in FIGS. 2-3. In other embodiments,computer programs are used to develop a pattern of layouts on a singlereticle and a corresponding exposure pattern for exposure of wafers bythe reticle.

[0079] As used herein, the term optical lithography refers processesthat include the use of visible, ultraviolet, deep ultraviolet, extremeultraviolet, x-ray, and other radiation sources for lithographypurposes.

Conclusion

[0080] The foregoing description of embodiments of the invention hasbeen provided for the purposes of illustration and description. It isnot intended to be exhaustive or to limit the invention to the preciseform disclosed. Many modifications and variations will be apparent. Theembodiments were chosen and described in order to best explain theprinciples of the invention and its practical application, therebyenabling others to understand the invention for various embodiments andwith various modifications as are suited to the particular usecontemplated. It is intended that the scope of the invention be definedby the following claims.

We claim:
 1. A method of fabricating a layer of material in anintegrated circuit (IC), the layer including a pattern, the layerdefined by a layout data, the method comprising: analyzing the layoutdata to determine whether substantial portions of the pattern are to bedefined using a phase shifting pattern; and responsive to the analyzing,configuring an optical lithography exposure system to have a setting ofa set of one or more optical parameters that control characteristics ofexposures, to expose at least a first mask pattern and a second maskpattern for use in defining the layer of material to use said settingfor exposing each mask pattern, and wherein the first mask patterncomprises an alternating aperture phase shifting pattern and wherein thesecond mask pattern comprises a trim pattern.
 2. The method of claim 1,wherein the analyzing comprises determining if all of the pattern on thelayer is defined using phase shifting.
 3. The method of claim 1, whereinthe layout data comprises a “full phase” design such that the first maskpattern comprises a “full phase” mask pattern.
 4. The method of claim 1,wherein the analyzing comprises determining if one or more of all of thepattern is defined using phase shifting, wherein a pattern is exposed onthe layer which can be characterized by one or more of the following: atleast eighty percent (80%) of the non-memory portions of the pattern aredefined by the phase shift pattern; at least eighty percent (80%) of apart of the floorplan in the pattern is defined by the phase shiftpattern; at least ninety percent (90%) of the pattern is defined by thephase shift pattern; all of the features in the critical path of thepattern are defined by the phase shift pattern; all features in thepattern except those features that are not phase shifted due to phaseconflicts are defined by the phase shift pattern; everything in thepattern except test structures are defined by the phase shift pattern;and everything in the pattern except dummy structures are defined by thephase shift pattern.
 5. The method of claim 1, wherein a pattern isexposed on the layer which can be characterized by having at leastninety-five (95%) of the pattern defined by the phase shift pattern. 6.The method of claim 1, wherein the optical lithography exposure systemcomprises at least one of a stepper and a scanner.
 7. The method ofclaim 1, wherein the first mask pattern and the second mask pattern areon a single reticle.
 8. The method of claim 1, wherein said set ofoptical parameters consists of the numerical aperture (N.A.), wavelength(λ) of radiation, partial coherency (σ), illumination configuration, anddefocus.
 9. The method of claim 1, wherein said set of opticalparameters comprise one or more of the numerical aperture (N.A.),wavelength (λ) of radiation, partial coherency (σ), illuminationconfiguration, and defocus.
 10. The method of claim 1, furthercomprising exposing the layer of material in the optical lithographyexposure system using a first dosing for the first mask pattern and asecond dosing for the second mask pattern, the first dosing and thesecond dosing in a ratio of 1.0 to r, r>0.0.
 11. The method of claim 10,wherein 2.0<=r<=4.0.
 12. The method of claim 10, wherein the first maskpattern and the second mask pattern are on a single reticle.
 13. Themethod of claim 12, wherein the exposing further comprises blading thefirst mask pattern and second mask pattern during the exposing to permitdifferent dosing.
 14. The method of claim 12, and wherein the singlereticle further includes a second instance of the second mask patternand wherein the exposing comprises exposing the layer of material to thesingle reticle in a pattern to cause a 1:2 exposure ratio between thefirst mask pattern and instances of the second mask patterns.
 15. Areticle for use in defining a pattern in a layer of material of anintegrated circuit (IC) production using optical lithography in anoptical lithography exposure system having a set of one or more opticalparameters that control characteristics of exposures, the reticle fordefining a layer of material in an IC, the reticle comprising at leasttwo patterns: a first pattern comprising a phase shifting mask; and asecond pattern comprising a trim mask, the first pattern defining asufficient amount of the layer of material using phase shifting to allowthe use of substantially the same settings of said set of one or moreoptical parameters for both the first pattern and the second pattern.16. The reticle of claim 15, wherein a pattern is exposed on the layerwhich can be characterized by one or more of the following: at leasteighty percent (80%) of the non-memory portions of the pattern aredefined by the phase shift pattern; at least eighty percent (80%) of apart of the floorplan in the pattern is defined by the phase shiftpattern; at least ninety percent (90%) of the pattern is defined by thephase shift pattern; all of the features in the critical path of thepattern are defined by the phase shift pattern; all features in thepattern except those features that are not phase shifted due to phaseconflicts are defined by the phase shift pattern; everything in thepattern except test structures are defined by the phase shift pattern;and everything in the pattern except dummy structures are defined by thephase shift pattern.
 17. The reticle of claim 15, wherein a pattern isexposed on the layer which can be characterized by having at leastninety-five (95%) of the pattern defined by the phase shift pattern. 18.The reticle of claim 15, wherein said set of optical parameters consistsof the numerical aperture (N.A.), wavelength (λ) of radiation, partialcoherency (σ), illumination configuration, and defocus.
 19. The reticleof claim 1, wherein said set of optical parameters comprise one or moreof the numerical aperture (N.A.), wavelength (λ) of radiation, partialcoherency (σ), illumination configuration, and defocus.
 20. The methodof claim 15, wherein substantially the same comprises within plus orminus 10%.
 21. The reticle of claim 15, wherein the reticle furtherincludes a third pattern substantially identical to the second pattern,such that the layer defined by a triple exposure comprising one exposureby the first pattern, one exposure by the second pattern, and a thirdexposure by the third pattern.
 22. The reticle of claim 15, wherein thereticle further includes a third pattern comprising a phase shiftingpattern, and wherein the first pattern for defining features oriented ina first direction in the pattern and the third pattern for definingoriented in a second direction features in the pattern, such that thelayer defined by a triple exposure comprising one exposure by the firstpattern, one exposure by the second pattern, and a third exposure by thethird pattern.
 23. An method of manufacturing an integrated circuit (IC)product comprising: defining at least one layer of material in the ICusing at least two mask patterns, the layer of material comprising apattern, the first mask pattern comprising a phase shifting pattern andthe second mask pattern comprising a trim pattern, the first patterndefining substantially all of the pattern of the layer of material andthe second pattern for protecting the pattern and clearing phaseshifting artifacts; exposing layer of material in an optical lithographyexposure system having a setting of a set of one or more opticalparameters that control characteristics of exposures, to the first maskpattern and the second mask pattern, where said setting is substantiallythe same while exposing the first and second mask patterns.
 24. Themethod of manufacturing an IC product of claim 23, wherein the firstmask pattern comprises a “full phase” mask. The method of manufacturingan IC product of claim 0, wherein the pattern on the layer of materialcan be characterized by one or more of the following: at least eightypercent (80%) of the non-memory portions of the pattern are defined bythe phase shift pattern; at least eighty percent (80%) of a part of thefloorplan in the pattern is defined by the phase shift pattern; at leastninety percent (90%) of the pattern is defined by the phase shiftpattern; all of the features in the critical path of the pattern aredefined by the phase shift pattern; all features in the pattern exceptthose features that are not phase shifted due to phase conflicts aredefined by the phase shift pattern; everything in the pattern excepttest structures are defined by the phase shift pattern; and everythingin the pattern except dummy structures are defined by the phase shiftpattern.
 25. The method of manufacturing an IC product of claim 23,wherein the pattern on the layer of material can be characterized byhaving at least ninety-five (95%) of the pattern defined by the phaseshift pattern.
 26. The method of manufacturing an IC product of claim23, wherein the optical lithography exposure system comprises at leastone of a stepper and a scanner.
 27. The method of manufacturing an ICproduct of claim 23, wherein the first mask pattern and the second maskpattern are on a single reticle.
 28. The method of manufacturing an ICproduct of claim 23, wherein said set of optical parameters consists ofthe numerical aperture (N.A.), wavelength (λ) of radiation, partialcoherency (σ), illumination configuration, and defocus.
 29. The methodof manufacturing an IC product of claim 23, wherein said set of opticalparameters comprise one or more of the numerical aperture (N.A.),wavelength (λ) of radiation, partial coherency (σ), illuminationconfiguration, and defocus.
 30. The method of manufacturing an ICproduct of manufacturing an IC product of claim 23, whereinsubstantially the same comprises within plus or minus 10%.
 31. Themethod of manufacturing an IC product of claim 23, wherein the exposingfurther comprises using a first dosing for the first mask pattern and asecond dosing for the second mask pattern, the first dosing and thesecond dosing in a ratio of 1.0 to r, r>0.0.
 32. The method ofmanufacturing an IC product of claim 31, wherein 2.0<=r<=4.0.
 33. Themethod of manufacturing an IC product of claim 23, wherein the firstmask pattern and the second mask pattern are on a single reticle. 34.The method of manufacturing an IC product of claim 33, and wherein theexposing further comprises blading the first mask pattern and secondmask pattern on the reticle during the exposing to permit differentdosing.
 35. The method of manufacturing an IC product of claim 33, andwherein the single reticle further includes a second instance of thesecond mask pattern and wherein the exposing comprises exposing thelayer of material to the instances of the mask patterns on the singlereticle in a sequence to cause a 1:2 exposure ratio between the firstmask patterns and instances of the second mask pattern.
 36. A method formanufacturing an integrated circuit, comprising: forming a layer ofresist on a wafer; exposing the layer to a first dose of radiationthrough a phase shifting pattern in a mask, the radiation characterizedby set of one or more parameters selected for exposure of the phaseshifting pattern; and exposing the layer to a second dose of radiationthrough a trim pattern in a mask, the radiation characterized by saidset of parameters.
 37. The method of claim 36, wherein said set ofparameters includes a parameter indicating partial coherence σ of theradiation at the layer.
 38. The method of claim 36, wherein said set ofparameters includes a parameter indicating the numerical aperture NA ofthe radiation at the layer.
 39. The method of claim 36, wherein said setof parameters includes a parameter indicating an axis of propagation ofthe radiation at the layer.
 40. The method of claim 36, wherein said setof parameters includes a parameter indicating an illuminationconfiguration of the radiation.
 41. The method of claim 36, wherein saidset of parameters includes a parameter indicating defocus of theradiation at the layer.
 42. The method of claim 36, wherein said set ofparameters includes parameters indicating numerical aperture NA of theradiation at the layer, partial coherence σ of the radiation at thelayer, an axis of propagation of the radiation at the layer, anillumination configuration of the radiation, and defocus of theradiation at the layer.
 43. The method of claim 36, wherein said firstdose and said second dose are different.
 44. The method of claim 36,wherein said phase shift pattern and said trim pattern are on a singlemask.
 45. The method of claim 36, wherein a pattern is exposed on thelayer which can be characterized by one or more of the following: atleast eighty percent (80%) of the non-memory portions of the pattern aredefined by the phase shift pattern; at least eighty percent (80%) of apart of the floorplan in the pattern is defined by the phase shiftpattern; at least ninety percent (90%) of the pattern is defined by thephase shift pattern; all of the features in the critical path of thepattern are defined by the phase shift pattern; all features in thepattern except those features that are not phase shifted due to phaseconflicts are defined by the phase shift pattern; everything in thepattern except test structures are defined by the phase shift pattern;and everything in the pattern except dummy structures are defined by thephase shift pattern.
 46. The method of claim 36, wherein a pattern isexposed on the layer which can be characterized by having at leastninety-five (95%) of the pattern defined by the phase shift pattern. 47.The method of claim 36, wherein said set of parameters comprisesparameters that are changed by a mechanical adjustment of an opticalelement.
 48. A method for manufacturing an integrated circuit,comprising: forming a layer of resist on a wafer in a first processstation; moving the wafer to a second process station including aradiation source, a mask and an optical path for exposing the wafer toradiation, the optical path being characterized by a set of opticalparameters including one or more of a wavelength λ of illumination,numerical aperture NA, coherence, illumination configuration, anddefocus; exposing, in the second process station, the layer to a firstdose of radiation through a phase shifting pattern in said mask using afirst setting of set of optical parameters; and exposing, in the secondprocess station, the layer to a second dose of radiation through a trimpattern in said mask using said first setting.
 49. The method of claim48, wherein said set of optical parameters includes the numericalaperture and partial coherence σ.
 50. The method of claim 48, whereinsaid set of optical parameters includes the numerical aperture NA,partial coherence σ, the illumination configuration, and the defocus.51. The method of claim 48, wherein said set of optical parametersincludes partial coherence σ as the coherence parameter.
 52. The methodof claim 48, wherein said first dose and said second dose have differentdosage levels.
 53. The method of claim 48, wherein a pattern is exposedon the layer which can be characterized by one or more of the following:at least eighty percent (80%) of the non-memory portions of the patternare defined by the phase shift pattern; at least eighty percent (80%) ofa part of the floorplan in the pattern is defined by the phase shiftpattern; at least ninety percent (90%) of the pattern is defined by thephase shift pattern; all of the features in the critical path of thepattern are defined by the phase shift pattern; all features in thepattern except those features that are not phase shifted due to phaseconflicts are defined by the phase shift pattern; everything in thepattern except test structures are defined by the phase shift pattern;and everything in the pattern except dummy structures are defined by thephase shift pattern.
 54. The method of claim 48, wherein a pattern isexposed on the layer which can be characterized by having at leastninety-five (95%) of the pattern defined by the phase shift pattern. 55.The method of claim 48, wherein said set of parameters comprisesparameters that are changed by a mechanical adjustment of an opticalelement.